Documents leaked revealing details of Zen 3 architecture. What will the new Ryzenes bring?

AMD confirmed that it will present architecture on October 8 Zen 3 and processors by default Ryzen 4000 (Vermeer). However, confidential documents leaked on the network reveal many interesting details about the next version of Zen, and although they do not reveal all the details, they seem to suggest that the third generation of this architecture will provide a strong foundation for the new Ryzen. These documents were published on the web by CyberPunkCat and they are Processor Programming Reference (PPR) for Family 19h, Model 21h B0, which is Zen 3. The previous architectures, i.e. Zen + and Zen 2, belong to Family 17h. AMD usually makes these types of documents available to developers after the premiere, so these are not very secret information about building architecture, but now, more than 3 weeks before the presentation, they are a good source of information.

The most important changes made to Zen 3 seem to be in the CCD / CCX configuration …

The most important changes made to Zen 3 seem to be configuration CCD/CCX. The new architecture will still be based on the construction of an MCM (multi-chip module) or a chiplet, using two CCD and one I / O kernels. Moreover, only one CCX block per CCD has been confirmed and this one will consist of eight cores that can work in single-threaded (1T) or double-threaded SMT (2T) mode. So this gives a maximum of 16 threads per CCX. This may suggest that Zen 3 will provide up to 16 cores, which is similar to the previous generation, where Ryzen 9 3950X has this number. Nevertheless, AMD may be preparing some surprises here, so better wait a while. The manufacturer also introduces changes to the cache subsystem. We get a total of up to 32 MB of L3 cache shared by all eight cores in CCX, instead of 16 MB for CCX, as is the case in Zen 2. In the current generation, the 32 MB third level cache on the CCD has to be shared by two separate modules. Ponato, Zen 3 will also feature a 512 KB L2 cache per core from the CCX framework and a total of 4 MB L2 cache on the CCD.

AMD also set out to improve the Scalable Data Fabric (SDF), which is a kind of backbone for the Infinity Fabric interface responsible for data transfer and coherence between the cores, memory controller and other I / O elements. Documents reveal that SDF will be able to handle 512 GB per DRAM channel. It also seems that some minor changes have been made to the Scalable Control Fabric (SCF), the second essential part of Infinity Fabric that deals with the main signaling. Zen 3 will also receive two Unified Memory Controllers (UMCs), each responsible for supporting one DRAM channel and two DIMM slots. It is also worth mentioning the native support for DDR4-3200 memory, so there will be no changes in this respect, just like in the Fusion Controller Hub (FCH). So it seems that in addition to speeding up the clocks, AMD has this time focused on improving the design of the MCM.


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