Complementary field-effect transistor (CFET) architectures are emerging as a prime candidate to replace traditional nanosheet designs from the A7 logic technology node onward, enabling standard cells of 4.5 tracks and below according to research presented by imec engineers Cassie Sheng, Hiroaki Arimura, and Naoto Horiguchi. Semiconductor researchers are pursuing two main integration tracks—monolithic CFET (mCFET) and sequential CFET (sCFET)—to stack pMOS and nMOS transistors vertically, thereby extending the classical CMOS logic roadmap deep into the ångström era.
Backside Contact Modules Improve Bottom pFET Drive Current and Yield
Contacting the source and drain junctions of bottom devices directly from the wafer backside delivers clear advantages over frontside contacting, according to imec’s findings. This backside approach reduces contact resistance for bottom devices and widens the process window for forming top device source and drain regions, as demonstrated by Cassie Sheng and colleagues at the 2024 VLSI symposium. To make this work without severe current leaks or structural defects, researchers developed a backside dielectric isolation (BDI) module.
Traditional BDI integration methods formed the isolation layer entirely from the wafer backside near the end of the manufacturing flow. That older approach caused high variability in the volume of bottom SiGe:B source and drain structures because the underlying silicon substrate seeded them during epitaxial growth. Furthermore, that volume consumed space needed for contact metal, driving up access resistance and causing yield losses. To fix this, imec demonstrated a novel scheme featuring both a frontside-formed BDI (FS-BDI) and a backside BDI structure, as presented at 2026 VLSI. By inserting an extra Ge-rich SiGe layer early in the process flow and later replacing it with a dielectric during middle-dielectric isolation processing, engineers isolated the bottom source and drain epitaxial structures from the silicon substrate.
This frontside BDI addition allowed researchers to achieve a fivefold improvement in the drive current ($I_s$) of bottom pFET devices compared to conventional integration schemes, according to 2026 VLSI data. Specifically, access resistance for bottom pFETs dropped from 1,753 $Omegamu$m down to 378 $Omegamu$m. Additionally, the survival yield of those bottom pFETs climbed from 45 percent to 85 percent.
Dipole-Based Gate Stack Integration Enables Multi-Vt Tuning for CFET
Integrated circuits require devices to operate at varying threshold voltages ($V_t$) to balance high-performance computing needs against ultra-low power consumption. In advanced stacked nanosheet and CFET architectures, however, the physical space between channels is extremely tight, preventing engineers from varying gate metal thicknesses to tune $V_t$.
Sequential CFET Architecture and Routing Enhancements
Beyond monolithic integration, sequential CFET (sCFET) development focuses on independent patterning of top and bottom devices using dedicated masks. While sCFET simplifies individual process steps compared to mCFET, it requires two wafer flips, which distorts the wafers and complicates precise front-to-back alignment. Despite these alignment hurdles, sCFET studies continue to advance both logic and SRAM scaling roadmaps.
Recent design-technology co-optimization (DTCO) studies presented by imec introduce a scalable architecture for sequential CFETs supporting both split-gate and common-gate configurations. At the same time, improved back-end-of-line (BEOL) routability has been demonstrated to support the strict area constraints of CFET standard cells.
Did you know? The European NanoIC pilot line targets the development of beyond-2nm systems-on-chip, with CFET development selected as a foundational technology to keep European semiconductor manufacturing at the cutting edge.
Frequently Asked Questions
What is a CFET transistor architecture?
A complementary field-effect transistor (CFET) is an advanced semiconductor architecture that stacks pMOS and nMOS transistors vertically on top of each other. This vertical stacking allows standard cells to shrink down to 3 tracks or lower, extending the classical CMOS logic roadmap beyond the limits of traditional nanosheet designs.
What is the difference between monolithic CFET and sequential CFET?
Monolithic CFET (mCFET) patterns and processes the vertical device structure with common top and bottom gates in a single sequence of steps. Sequential CFET (sCFET) patterns the top and bottom devices independently using separate masks and involves two wafer flips, making process steps simpler individually but introducing strict wafer-alignment challenges.
How does the dipole-middle gate stack approach protect CFET devices?
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