AMD is shifting its GPU design strategy as semiconductor manufacturing hits a physical scaling wall for SRAM. According to industry reports, TSMC’s move to prioritize logic density over cache scaling in its 3nm process has forced AMD to move away from large, integrated cache pools. Future architectures, including RDNA 5, will rely more on advanced data compression logic to maintain performance, as the cost of traditional SRAM continues to rise significantly compared to previous generations.
The End of SRAM Scaling at 3nm
For years, SRAM (Static Random Access Memory) served as the primary tool for GPU designers to overcome bandwidth bottlenecks. When AMD launched the RDNA 2 architecture, it integrated 128 MB of “Infinity Cache” directly onto the Navi 21 die. This allowed the company to avoid the high costs and power consumption associated with wider memory buses and extra memory chips.
However, that scaling trend has stalled. While TSMC’s 7nm and 5nm processes allowed for continued shrinking of logic and cache, the 3nm transition marks a departure. TSMC has prioritized scaling logic to maintain processing speed and energy efficiency, effectively leaving SRAM density stagnant. Consequently, the cost per megabyte of SRAM is rising, with estimates suggesting that 64 MB of cache on a 3nm process could cost significantly more than the same capacity on 4nm.
The shift toward 3nm manufacturing means that simply increasing cache size is no longer an economically viable path for performance gains. Manufacturers are now forced to innovate through software and compression algorithms to do more with less physical silicon.
RDNA Evolution: From Capacity to Efficiency
AMD’s architectural evolution highlights a clear pivot from brute-force cache capacity to algorithmic efficiency. The RDNA 2 architecture (Radeon RX 6900 XT) utilized a massive 128 MB of on-die SRAM. By the time RDNA 3 arrived, the design had transitioned to a chiplet-based approach, utilizing 64 MB of faster cache to achieve comparable performance levels.
With RDNA 4, AMD further refined this, utilizing complex compression algorithms to match the performance of the 96 MB cache found in the RX 7900 XTX while using only 64 MB of SRAM. Data suggests that between RDNA 2 and RDNA 4, the efficiency of performance per megabyte of SRAM has roughly tripled. This trend is expected to continue with RDNA 5, where the focus shifts almost entirely to reducing the volume of data that needs to be moved across the chip.
The RDNA 5 Strategy: Logic Over Memory
With the upcoming RDNA 5 architecture, expected in the second half of 2027, AMD is doubling down on compression. By keeping data compressed, the GPU requires less space in the cache, allowing more information to remain “on-chip” rather than being sent to slower external VRAM.
Reports indicate a significant change in how these chips will be binned. In previous generations, such as the RX 6900 XT or RX 9070 XT, all models based on a specific GPU die shared the same total cache capacity. Designers typically included a “buffer” of extra SRAM to account for manufacturing defects, which could be disabled without impacting the marketed capacity. For RDNA 5, sources suggest AMD may reduce this redundancy. This could lead to a tiered market where chips from the same silicon production line feature varying amounts of usable L2 cache, depending on the number of defective sectors found during manufacturing.
Projected GPU Cache Configurations
| GPU Model | L2 Cache | Bus Width |
|---|---|---|
| AT0 | 64 MB | 512-bit |
| AT2 | 24 MB | 192-bit |
Frequently Asked Questions
- Why is SRAM not shrinking like other components?
- TSMC has made a strategic choice to focus manufacturing resources on scaling logic density, which directly impacts clock speeds and power efficiency, rather than SRAM, which has reached a point of diminishing returns in recent process nodes.
- How does data compression help GPU performance?
- Compression allows more data to fit into the existing cache. This reduces the number of times the GPU must access the slower external memory (VRAM), which saves power and improves overall throughput.
- When will RDNA 5 products be available?
- Current industry expectations point to a release in the second half of 2027, though market volatility regarding memory pricing could influence the final timeline.
What are your thoughts on the shift toward smaller caches and higher compression? Join the conversation in the comments below or subscribe to our newsletter for the latest updates on GPU architecture developments.
