Huawei’s latest Kirin 9030 processor, manufactured by SMIC using its third-generation 7 nm (N+3) process, marks a significant shift in China’s semiconductor strategy. According to a teardown by the SemiAnalysis STEEL lab, the chip achieves logic density comparable to TSMC’s N6 node by utilizing aggressive DUV multi-patterning and design-technology co-optimization (DTCO). While this allows Huawei to maintain domestic silicon production despite export controls, the process results in higher manufacturing complexity, increased costs, and lower power efficiency compared to leading-edge alternatives from Apple, Qualcomm, and MediaTek.
How does SMIC’s N+3 process compare to TSMC N6?
SMIC has reached N6-class logic density by pushing deep ultraviolet (DUV) immersion lithography to its physical limits. Analysis from SemiAnalysis indicates that SMIC’s N+3 node features a transistor density of 113.4 MTr/mm², slightly exceeding the 107.7 MTr/mm² measured in TSMC’s N6-based MediaTek Helio G99. However, SMIC achieves this density through a more complex integration path. While TSMC’s N6 relies on established process maturity, SMIC employs self-aligned quadruple patterning (SAQP) for its 32.5 nm metal pitch, a move that increases mask counts and overlay sensitivity. This contrast highlights that while China has narrowed the density gap, it has done so by accepting higher process risk and lower yields than foundries using EUV lithography.
The Kirin 9030 features a 32.5 nm local metal pitch, which is actually tighter than the 36 nm pitch found in Intel’s Panther Lake CPUs on the 18A node. However, this metric is a specific design choice rather than an indicator of overall chip performance.
Why is Huawei shifting toward 3D stacking?
Huawei is adopting “LogicFolding” to compensate for the lack of access to extreme ultraviolet (EUV) lithography. As reported by Huawei at ISCAS 2026, this strategy involves vertical 3D stacking of active logic tiers to shorten signal paths and reduce buffer requirements. By moving parts of the same logic block across multiple bonded dies, Huawei aims to recover the frequency and efficiency gains that are currently limited by planar process scaling. This architectural pivot suggests that Huawei’s future roadmap will prioritize system-technology co-optimization (STCO) over pure foundry-level transistor shrinking, aiming to reach 14A-equivalent package density by 2031.
How are export controls shaping the Chinese semiconductor ecosystem?
US-led export controls have forced a transition from reliance on Western electronic design automation (EDA) tools to a domestic development model. According to SemiAnalysis, Huawei has successfully deployed in-house design flows to iterate on the Kirin 9020 and 9030. This shift is not confined to Huawei; government directives are encouraging the transfer of SMIC’s N+2 and N+3 process knowledge to other domestic foundries like HLMC and Hua Hong. While this does not close the performance gap with global leaders, it creates a more resilient domestic supply chain for AI inference, networking, and security-critical hardware.
When evaluating chip performance, look beyond the node name. Even if SMIC N+3 matches the density of TSMC N6, the “voltage-frequency curve” and transistor budget of the design ultimately dictate real-world battery life and thermal stability.
Frequently Asked Questions
- Is SMIC’s N+3 process as good as TSMC’s leading-edge nodes? No. While N+3 matches the density of the older TSMC N6, it remains significantly behind current flagships from Apple and Qualcomm, which utilize N4 and N3P nodes for superior performance per watt.
- What is LogicFolding? It is a 3D integration technique where Huawei stacks active logic dies face-to-face to shorten signal paths, allowing for higher clock speeds without needing to shrink the base transistor size.
- Does the Kirin 9030 use EUV lithography? No. The SMIC N+3 process relies entirely on DUV multi-patterning, specifically using SAQP to achieve its density metrics.
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