TSMC is struggling to keep pace with unprecedented demand for AI and high-performance computing (HPC) chips, creating a supply chain bottleneck that is forcing major customers to seek advanced packaging capacity elsewhere. While the Taiwanese foundry maintains a lead in CoWoS (Chip-on-Wafer-on-Substrate) technology, competitors like Intel and various Taiwanese packaging firms are capturing overflow orders, according to reports from the Commercial Times.
The CoWoS Bottleneck and Market Spillover
TSMC’s CoWoS technology has become the industry standard for AI hardware, but the sheer volume of orders from companies like NVIDIA, AMD, and Amazon AWS has outstripped the foundry’s current production capacity. Because TSMC is prioritizing its most profitable processes and highest-end clients, orders that cannot be accommodated are spilling over to other providers.
This shift is benefiting a range of packaging and testing companies. According to industry reports, firms including ASE, SPIL, Powertech, and KYEC are absorbing excess demand.
Pro Tip: When evaluating semiconductor supply chains, watch for “capacity reservation” announcements. Major AI players often reserve production space years in advance, which can signal long-term supply constraints for smaller hardware developers.
Intel’s Strategic Push into Advanced Packaging
Intel is positioning itself as a primary alternative to TSMC by aggressively expanding its advanced packaging footprint. The company is promoting its EMIB technology, which it claims offers distinct performance advantages over traditional CoWoS methods.
Intel’s expansion is bolstered by support from the U.S. government, aligning with broader efforts to onshore semiconductor manufacturing. Reports indicate that NVIDIA, a primary TSMC customer, may shift some advanced packaging orders for its future “Feynman” GPU architecture to Intel. This move highlights the competitive pressure on TSMC to maintain its dominance while navigating the constraints of its five existing advanced packaging plants in Taiwan and its planned facilities in Arizona.
Future Scaling of AI Hardware Production
The demand for AI chips is not slowing down. AMD, for instance, is already utilizing TSMC’s CoWoS for its EPYC Venice chips on the N2P node and has confirmed plans to use these packaging technologies for upcoming MI400 and MI500 series chips. These components are intended for large-scale hyperscaler and Frontier-Scale platforms.
To address these needs, TSMC is actively expanding its footprint. The company operates facilities in Hsinchu, Southern Taiwan, Taoyuan Longtan, Central Taiwan, and Miaoli Zhunan. However, with wafer prices rising sharply due to supply constraints, the industry is closely watching whether these expansions can keep pace with the exponential growth of the global AI landscape.
Did you know?
TSMC’s “12-fab Expansion” plan includes the construction of two major plants in Arizona. These U.S.-based facilities are intended to bolster global supply chain resilience, though they remain part of a larger, complex logistics puzzle involving both domestic and international production sites.
Frequently Asked Questions
Why is TSMC struggling to meet AI chip demand?
The demand for CoWoS advanced packaging has surged beyond current production capacity. While TSMC is building new facilities in Taiwan and the U.S., the rapid adoption of AI and HPC hardware has outpaced the speed at which these specialized plants can come online.
Which companies are benefiting from TSMC’s overflow orders?
Intel is emerging as a major competitor with its EMIB technology. Additionally, Taiwanese testing and packaging firms such as ASE, SPIL, Powertech, and KYEC are taking on increased volume as customers diversify their supply chains.
What is CoWoS technology?
CoWoS (Chip-on-Wafer-on-Substrate) is a packaging technology that allows multiple chips to be mounted on a single substrate.
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