Reconfigurable ternary inverters utilizing charge-trapping-layer threshold voltage modulation achieve a balanced combination of power consumption, switching speed, functional flexibility, and complementary metal-oxide-semiconductor compatibility, according to device engineering research. Designing multi-valued logic circuits has long forced engineers to choose between power efficiency and speed. Now, a proposed silicon-oxide-nitride-oxide-silicon FinFET architecture offers a path forward by allowing dynamic switching between binary and ternary operations.
Overcoming CMOS-Based Ternary Inverter Limitations
Traditional multi-valued logic circuits struggle to simultaneously achieve competitive power consumption, fast switching speeds, and functional flexibility within a standard complementary metal-oxide-semiconductor framework.
To tackle these bottlenecks, researchers proposed a reconfigurable ternary inverter leveraging charge-trapping-layer-induced threshold voltage modulation. This mechanism allows precise control of voltage transfer characteristics. By selectively integrating charge-trapping layers into different transistor types, the voltage transfer characteristics can be modulated either vertically or horizontally depending on device location. This structural control gives designers exact command over intermediate logic levels and switching boundaries.
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Simulating Performance Across Transistor Configurations
Validating these designs requires rigorous modeling. According to technology computer-aided design-based mixed-mode simulations calibrated with experimental data, the integration location of the charge-trapping layer strongly influences both voltage transfer characteristic modulation and overall circuit performance.
Performance metrics vary significantly depending on where the technology is applied:
- Low-Threshold-Voltage Transistor Integration: Enables binary and ternary reconfiguration while maintaining a $V_{DD}/2$ power consumption of 173 nW. It achieves average propagation delays of 5.10 ns under ternary operation and 4.77 ns under binary operation.
- High-Threshold-Voltage Transistor Integration: Exhibits a pronounced propagation-delay penalty under ternary operation, underscoring the critical nature of precise placement in reconfigurable ternary inverter design.
These findings point to a general design strategy for voltage transfer characteristic engineering. Charge-trapping layer placement serves as a primary design parameter for controlling modulation modes and balancing associated performance trade-offs in multi-valued logic circuits.
Maintaining Compatibility with Silicon CMOS Technology
However, the incorporation of a silicon-oxide-nitride-oxide-silicon FinFET structure provides improved electrostatic control while maintaining full compatibility with conventional silicon complementary metal-oxide-semiconductor technology.
The use of established FinFET foundations means these dynamic ternary circuits could theoretically integrate into existing production lines once commercial scaling begins.
Frequently Asked Questions
What is a ternary inverter?
How does charge-trapping-layer modulation work?
It involves selectively integrating charge-trapping layers into specific transistors to tune threshold voltages, which alters the voltage transfer characteristics of the circuit.
Why is silicon CMOS compatibility important?
Compatibility with conventional silicon complementary metal-oxide-semiconductor technology allows new circuit designs to be manufactured using existing semiconductor fabrication infrastructure.
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